MIPS Classic Cores target every design need from entry level to high performance across embedded designs, digital consumer, broadband access and networking, and state-of-the-art communications.

 

MIPS32 1074Kc/f

High performance cache coherent multiprocessor system (CPS) supporting up to four MIPS32 1074K processor cores.

The 1074K CPS is based on the combination of two high-performance technologies—coherent multiprocessing, and the superscalar, multi-issue 15 stage pipeline Out-of-Order MIPS32 74K® processor core as the base CPU.

Multi-CPU coherence is enabled by a Coherence Manager Unit, a high throughput fabric supporting internal 256-bit datapaths and connection to an optional L2 cache controller. 1074K single core delivers a performance of 1.93 DMIPS/MHz and 3.49 Coremarks/MHz. The 1074Kf version includes an IEEE754 compliant Floating Point Unit, supporting both single and double precision datatypes.

 

Documentation

  Boot-CPS: Example Example Boot Code for MIPS® Cores [Register or login]
  MIPS32® 1074K™ Coherent Processing System Datasheet [Register or login]
  MIPS32® 1074K™ CPU Family Software User's Manual [Register or login]


MIPS32 1004Kc/f

High performance cache coherent multiprocessor system (CPS) supporting up to four MIPS32 1004K multi-threaded processor cores and an optional coherent I/O port.

The 1004K processor core is based on a 9-stage pipeline design with support for up to two hardware threads/core. Multi-CPU coherence is enabled by a Coherence Manager Unit, which also can connect to an optional L2 cache controller with 256-bit datapath.

1004K single core delivers a performance of 1.6 DMIPS/MHz and 3.05 Coremarks/MHz. The 1004Kf version includes an IEEE754 compliant Floating Point Unit, supporting both single and double precision datatypes.

 

Documentation

  The MIPS32® 1004K™ Product Brief [Register or login]
  MIPS32® 1004K™ CPU Family Software User's Manual [Register or login]
  MIPS32® 1004K™ Coherent Processing System Datasheet [Register or login]
  Programming the MIPS32® 1004K™ Coherent Processing System Family [Register or login]


MIPS32 74Kc/f

The MIPS32 74K is based on a superscalar asymmetric dual-issue pipeline microarchitecture with out-of-order (OoO) instruction dispatch and completion.

The implementation features a 15-stage pipeline to achieve high synthesizable frequencies, and supports up to 4 instructions fetched per cycle, plus up to 4 instructions issued per cycle. The 74Kc/f incorporates the MIPS® DSP Module Rev2 for enhanced signal processing capabilities.

The 74Kc/f includes an OCP Bus Interface Unit and connection to an optional L2 cache controller and delivers a performance of 1.93 DMIPS/MHz and 3.48 Coremarks/MHz. The core also includes an IEEE754 compliant Floating Point Unit, supporting both single and double precision datatypes.

 

Documentation

  Architectural Strengths of the MIPS32® 74K® Core Family [Register or login]
  MIPS32® 74Kc™ Processor Core Datasheet [Register or login]
  MIPS32® 74Kf™ Processor Core Datasheet [Register or login]
  Programming the MIPS32® 74K® Core Family [Register or login]
  Programming the MIPS® 74K® Core Family for DSP Applications [Register or login]
  MIPS32® 74K® Processor Core Family Software User’s Manual [Register or login]
  74K BDTi DSP White Paper [Register or login]
  Breaking the Gigahertz Speed Barrier with an Automated Flow Using Synopsys ICC Compiler [Register or login]


MIPS32 34Kc/f

The MIPS32 34K is a 9-stage pipeline multi-threaded processor core with support for up to two Virtual Processing Elements (VPE) and nine Thread Context (TC)s per VPE.

Processing multiple software threads in parallel, 34K cores mask the effect of memory latency to deliver instant 20-40% gains in system performance and cost savings, with a very modest increase in die size.

Depending on the application, the 34K core can implement symmetric multiprocessing across two VPEs. Alternatively, each VPE can run a separate operating system. The 34Kc/f also includes an optional the MIPS DSP Module, programmable L1 cache controller and OCP Bus interface Unit.

The 34K processor core delivers a performance of 1.6 DMIPS/MHz and 3.05 Coremarks/MHz. The core includes an IEEE754 compliant Floating Point Unit, supporting both single and double precision datatypes.

 

Documentation

  MIPS32® 34K™ Processor Core Family Software User’s Manual [Register or login]
  MIPS32® 34Kc™ Processor Core Datasheet [Register or login]
  MIPS32® 34Kf™ Processor Core Datasheet [Register or login]
  MIPS® MT Principles of Operation [Register or login]
  Programming the MIPS32® 34K™ Core Family [Register or login]


MIPS32 24K

The MIPS32 24K is a 8-stage pipeline processor core that implements the MIPS32 Release 2 Architecture, including support for dynamic branch prediction, optional MIPS DSP module, MIPS16e Instruction Set Architecture and programmable L1 cache controller.

The 24K includes an OCP Bus Interface Unit, EJTAG debug and MIPS Trace support is provided. The processor core delivers a performance of 1.6 DMIPS/MHz and 3.1 Coremarks/MHz. The 24Kf version includes an IEEE754 compliant Floating Point Unit, supporting both single and double precision datatypes.

 

Documentation

  MIPS32® 24K® Processor Core Family Software User’s Manual v3.11 [Register or login]
  MIPS32® 24Kc™ Processor Core Datasheet v4.00 [Register or login]
  MIPS32® 24Kf™ Processor Core Datasheet v4.00 [Register or login]
  Programming the MIPS32® 24K® Core Family v4.63 [Register or login]
  The MIPS32® 24KE™ Core Family: High-Performance RISC Cores with DSP Enhancements [Register or login]
  Working with ScratchPad RAMs for MIPS32® 24K® and 34K® Cores [Register or login]

 

MIPS32 M14K/c

The MIPS32 M14K family of cores have a high-performance, compact, low-power design with features that are optimized to deliver a superior solution for microcontroller (MCU) and real-time embedded system applications. The MIPS32 M14K™ family includes the MIPS32 M14K and MIPS32 M14Kc processor cores, the first MIPS32-compatible processor cores to execute the new microMIPS™ code compression Instruction Set Architecture (ISA).

The M14K core includes real time performance, flash memory acceleration, reduced interrupt latency, features required for best in class MCU designs. The core includes a programmable instruction, data cache controller and Translation Lookaside Buffer Memory Management Unit (TLB MMU), enabling high performance execution of Linux and other virtual memory operating systems. M14K processor cores deliver a performance of 1.57 DMIPS/MHz and 3.4 Coremarks/MHz.

 

Documentation

  MIPS32® M14K™ Processor Core data sheet [Register or login]
  MIPS32® M14K™ Processor Core Family Software User’s Manual [Register or login]
  MIPS32® M14Kc™ Processor Core Family Datasheet [Register or login]
  MIPS32® M14Kc™ Processor Core Family Software User’s Manual [Register or login]


MIPS32 M4K/4K

The MIPS32 M4K/4K family includes MIPS32 4K, MIPS32 4KSd, MIPS32 4KE and MIPS32 M4K 32-bit synthesizable processor cores.

The MIPS32 M4K/4K family of 32-bit synthesizable core provides a highly performance-efficient, feature-rich solution for a broad range of real-time, cost-sensitive embedded system applications. Based on the well-proven MIPS Release 2 architecture, the M4K core is designed around a 5-stage pipeline, SRAM interface and comprehensive debug features. In addition, the M4K core includes the MIPS16e Application Specific Extension (ASE), reducing code size by up to 40%. The M4K processor core in MIPS32 mode delivers a performance of 1.6 DMIPS/MHz and 3.4 Coremarks/MHz.

 

Documentation

  MIPS32® 4K® Processor Core Family Software User’s Manual [Register or login]
  MIPS32® M4K® Processor Core Data Sheet [Register or login]
  MIPS32® M4K® Processor Core Software User’s Manual [Register or login]