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PowerVR Graphics


PowerVR™ visual IP technologies have been developed over more than two decades to meet the most demanding requirements of high volume mobile and consumer applications. With their roots in arcade platforms and digital TV, PowerVR visual technologies lead the world in delivering exceptional levels of performance while delivering low power, small silicon area and high levels of system latency tolerance when integrating with unified memory and other shared resources.

PowerVR Graphics

PowerVR graphics technology is based on a concept called Tile Based Deferred Rendering (TBDR). In contrast to Immediate Mode Rendering (IMR) used by most graphics engines in the PC and games console worlds, TBDR focuses on minimising the processing required to render an image as early in the processing of a scene as possible, so that only the pixels that actually will be seen by the end user consume processing resources. This approach minimizes memory and power while improving processing throughput but it is more complex. Imagination Technologies has refined this challenging technology to the point where it dominates the mobile markets for 3D graphics rendering, backed up by an extensive patent portfolio.

The latest generation of this advanced architecture is the PowerVR Series6 family of graphics IP cores. Based on a scalable number of compute clusters, the PowerVR Series6 ‘Rogue’ architecture is designed to target the requirements of a growing range of demanding markets from mobile to the highest performance embedded graphics including smartphones, tablets, PC, console, automotive and TV. Using these arrays of programmable computing elements, PowerVR Series6 cores deliver class-leading graphics and GPU Compute efficiency while minimising power and bandwidth demands.

The PowerVR Series6 family of GPUs delivers a significant portfolio of new technologies and features, including: advanced scalable compute cluster architecture; high efficiency compression technology including lossless image and parameter compression and the widely respected PVRTC2™ texture compression; an enhanced scheduling architecture; dedicated housekeeping processor based on Imagination’s Meta technology; and a new generation Tile Based Deferred Rendering architecture. These features combine to produce a highly latency tolerant architecture that consumes the lowest memory bandwidth in the industry while delivering the optimal performance per mm2 or per mW depending on configuration.

PowerVR Series6 GPUs deliver full support for all popular and emerging GPU compute APIs including OpenCL 1.x and Renderscript Compute, delivering an optimal balance of performance versus power consumption for mobile and embedded devices. Members of the Series6 family are designed to support the features of the latest graphics APIs including OpenGL ES 3/2/1.1, OpenGL 3.x/4.x, and full WHQL-compliant DirectX10, with certain family members extending their capabilities to DirectX11.1 functionality.

Completing the portfolio of graphics IP cores is the PowerVR SGX Series5 and Series5XT families of graphics IP cores. With a level of scalability from 1 to 8 pipelines and beyond, based on the unique Universal Scalable Shader Engine (USSE), PowerVR SGX brings fully compliant OpenGL ES 2.0 shader-based graphics capability to mobile and consumer platforms. Series5XT architecture further builds on the underlying strengths of Series5, delivering significant performance advantages through increased floating point and instruction throughput as well as natively supported YUV and color space conversion.

This architecture also significantly further extends the scalability of the architecture by enabling multi-processor implementations, with up to 16 core instantiations possible that deliver better than 95% linear performance scaling of both geometry and pixel processing resources. The total Series5 and Series5XT portfolio therefore enables the industry’s broadest range of performance/area options, from the smallest single pipe SGX520 core up to the 64-pipe SGX554MP16. All popular APIs and OS are supported by all SGX cores, including OpenGL ES 2.0/1.1, OpenVG 1.1, OpenGL 2.0/3.0 and DirectX 9/10.1 on Linux, Android, WinCE/Windows Mobile and Windows 7/Vista/XP.

Tile Based Deferred Rendering

PowerVR graphics technology is based on a concept called Tile Based Deferred Rendering (TBDR). In contrast to Immediate Mode Rendering (IMR) used by most graphics engines in the PC and games console worlds, TBDR focuses on minimising the processing required to render an image as early in the processing of a scene as possible, so that only the pixels that actually will be seen by the end user consume processing resources. This approach minimizes memory and power while improving processing throughput but it is more complex. Imagination Technologies has refined this challenging technology to the point where it dominates the mobile markets for 3D graphics rendering, backed up by an extensive patent portfolio.

All parts of the TBDR are fully handled in hardware and are completely invisible to software developers ensuring maximal compatibility and performance. PowerVR’s unique smart parameter management technology allows TBDR rendering in limited memory footprints ensuring compatibility of high complexity titles without excessive memory usage.

PowerVR Texture Compression (PVRTC)

Texture compression reduces application file size and download times; it also dramatically improves runtime performance and power consumption on mobile platforms such as smartphones and tablets by keeping bandwidth consumption to an absolute minimum.

The highly acclaimed PVRTC lossy texture compression (TC) format is one of the most widely used texture compression formats in the mobile industry today, implemented in more than 600m devices. It is fully accelerated in hardware on all Series5/5T (SGX) and PowerVR Series6 'Rogue' GPU cores. PVRTC enables both RGB and RGBA formats to be compressed into 2 or 4 bits per pixel versus the standard 32 bits formats given a 8:1 up to 16:1 compression ratio.

PVRTC2 is a major compression technology upgrade and builds on the many strengths of PVRTC, adding a wide range of new features on Series5XT and Series6 devices including:

  • Improved image quality, especially for textures with high contrast, large areas of significant colour discontinuity, or boundaries of non-tiling textures
  • Better support for pre-multiplied textures
  • Support for arbitrary sized NPOT (Non Power Of Two) textures
  • Sub-Texturing

PowerVR Lossless Compression (Rogue Architecture only)

To further optimise the dataflow of TBDR PowerVR’s Rogue architecture has added lossless compression to the intermediate data store required as part of tile based rendering. Building on already existing market-leading features such as macrotiling (optimal memory management), perfect culling (including small polygons) and perfect tiling (perfect sorting avoids setup/bandwidth overhead) the addition of lossless compression ensures that bandwidth overhead for tiling is kept to an absolute minimum.

Where PVRTC enables lowest memory bandwidth for developer lossy pre-compressed textures there are many market segments where loss of quality is not acceptable or where the target device market is highly fragmented making device or API specific compression impossible. To ensure lowest memory bandwidth irrespective of developer and market limitations, the PowerVR’s Rogue Architecture add hardware based loss-less compression technology to ensure that all texture formats see a reduction in bandwidth and power usage independent of developers choices and abilities. This functionality also reduced the read/write bandwidth usage cost of off-screen render targets which are extremely common in both game and especially GUI applications where all off-screen render targets of widgets and applications are compressed before being processed by the 3D compositing GUI engine. PowerVR’s lossless compression is fully integrated into the hardware and is transparent to developers with no requirements or overhead on the application side.

PowerVR USSE and USC Architecture

PowerVR Series5 cores are based on a Unified Scalable Shader Engine (USSE) which enables efficient performance scaling from 1 to 4 pipelines. The PowerVR Series5XT cores extend the feature set and performance of the USSE (version 2) by doubling the floating point throughput capabilities and extending the scalability to 8 pipelines. The PowerVR Series6 'Rogue' cores deploy a pipeline cluster approach, the Unified Scalable Cluster (or USC), with each cluster containing up to 16 pipelines and cores containing from 1 up to 8 clusters.

Both USSE and USC architectures are based on a massively multi-threaded and multi-tasking approach which is hardware managed and load balanced by using a data driven execution model to ensure the highest possible utilisation efficiency of the Arithmetic Units within the pipelines. This approach schedules tasks based on data availability and enabled switching between independent processing tasks to ensure that data dependency stalls are avoid at all costs.

PowerVR Scalability

All PowerVR cores offer full linear scalability based on pipelines and clusters with all critical performance characteristics scaling along with the increase in computational power. PowerVR S5XT and later cores further extend this scalability by adding a fully hardware load balanced approach to multi-core scalability. All processing resources scale linear with PowerVR multi-core approach including geometry, pixel as well a GPU compute workloads based on a hierarchical demand based processing approach which assigns geometry blocks, tiles and GPU compute blocks optimally to the available processing resources.

PowerVR Microkernel Firmware

All PowerVR cores are managed using a software firmware which controls all higher level events at the GPU level. This approach offers numerous advantages including full offloading of the main host CPU of virtually all interrupt handling while fully maintaining maximal flexibility where the GPU execution is based on a software controlled firmware. On PowerVR S5/5XT cores the microkernel firmware is executed on the USSE pipelines to ensure optimal silicon area utilisation where S6 cores move the microkernel execution to a dedicated C-programmable multi-threaded microcontroller which enables full debugging functionality of the GPU core. The software based management of the GPU core ensures flexibility to adapt to future market requirements (e.g. OpenCL for PowerVR cores) and enables minimal CPU load (all interrupts handled locally) as well as optimal performance (priority based execution of GPU tasks). The Microkernel also facilitates advanced power management features by signalling back workloads to DVFS and power gating logic within the SoC.



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