Performance and power/area are generally conflicting design goals and represent the Yin and Yang of SoC design.  There’s a constant push and pull with every generation of SoCs, and just when you think you’ve achieved the perfect harmony, the target moves on you!

Actually, it’s rather amazing how rapidly SoC performance targets shift and how yesterday’s “high-end” performance is now today’s “mid-range.”

Take for example the targets for smartphones.  They have seen such a rapid rate of adoption that a nascent, but fast-growing market for entry-level smartphones has emerged.  These are the sub-$100 models that don’t have all the bells and whistles of the high-end phones but still need a decent amount of performance to support the more common features.  Several of the early low-cost smartphone models use single-core processors, but newer designs are targeting multi-core, whether they do only apps processing, baseband processing, or a combination of both.  Good midrange multi-core performance is desired, but given the high-volume and mobile aspects of these devices, low cost and low power are also heavily desired design goals.

mips_interAptiv_architecture

Entry-level smartphones may be a good poster-child for the “Yin and Yang” application, but these are not the only devices that need area- and power-efficient mid-range multicore performance.  Driven by broadband, mobility and new applications, SoCs for SSD controllers, residential gateways, and automotive infotainment electronics have also shown an increase in performance requirements that require multi-core.  While these applications don’t necessarily demand the highest levels of performance, they still need very good mid-range capabilities.  And getting just the right mix of power and performance can often be more challenging than designing something just based on performance alone, given the tight design constraints.

We are excited about MIPS’ new interAptiv family of multi-threaded, multiprocessor CPUs because it delivers the efficient mid-range, multi-core performance needed in a variety of embedded devices, while simultaneously offering low power and low cost.  It’s ideal for the aforementioned applications and others with similar profiles.  With the interAptiv cores, this efficiency comes largely from the use of multi-threading, which really shows its value when applications are highly parallel and subject to pipeline stalls from long memory accesses.  The net result with interAptiv cores is that designs can realize the highest levels of performance on a per-unit area and per-unit power basis.  From this standpoint, interAptiv cores run circles around competitive cores in the same class.  Factor in the multi-core support provided with interAptiv, and this means now you have a highly SCALABLE and efficient multi-processing platform.

mips interAptiv

One of the key improvements in interAptiv cores over previous generations of MIPS’ multi-threaded cores is in the multi-core performance.  As I said earlier, more and more mid-range designs are going multi-core, so making sure the block that connects the cores together has good performance is suddenly at the forefront.  The interAptiv core uses MIPS’ 2nd generation coherence manager (CM) with integrated L2 cache.  With the integration of the L2 cache and other improvements, the CM delivers significantly improved latencies and better system throughput.

Power management also got a boost in the interAptiv cores, with intelligent way selection in L1 ICACHE, ability to do 32-bit accesses to the L1 DCACHE and DSPRAMs, and the ability to turn off the core clock on outstanding bus requests.  This comes along with the other power management features found in our prior generation of multi-threaded/multi-core offerings, including cluster level power control, which provides voltage and clock gating on a per core basis.

And for those designers working on SoCs for applications requiring higher reliability, the interAptiv core offers ECC on L1 DCACHE and DSPRAM memories.  This is good for applications such as storage or driver assistance in automotive where data integrity may be a higher priority relative to other applications.

So while we can’t completely eliminate the balancing act of blending performance with power/cost efficiency, (sorry, there’s not yet a push button solution for that) we can surely make the process a lot easier with the interAptiv cores.  So learn how to balance your Yin and Yang with interAptiv cores today by going to the interAptiv product page on the MIPS website!

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