It has been a thrilling year for MIPS processors. We’ve seen exciting new designs from Loongson Technology while Cavium has introduced several OCTEON III and Fusion-M processors that cover the mid-range segment of the networking market. Multiple customers are now shipping products with Warrior CPUs, from high-end application processors to microcontrollers and embedded SoCs. Announced or imminent chips include those from Baikal Electronics, Microchip Technology, Altair Semiconductor, Mobileye, and Standing Egg.

MIPS Warrior CPUs are gaining momentum as customers see them in action and recognize the differentiation they can provide for a myriad of applications, based on unique features such as hardware multithreading, OmniShield multi-domain security across the lineup, and more. We’re ramping up to an exciting 2016 with strong technology and a compelling roadmap from 32-bit MCUs for deeply embedded applications and IoT to 64-bit Warriors with HSA support.

Today Imagination is marking a comeback for the MIPS64 architecture by introducing the new MIPS P6600 CPU, a straightforward upgrade for customers looking for a high-performance, 64-bit P-class Warrior CPU. The launch of this new 64-bit processor comes at a time when the industry is expressing a growing demand for real alternatives in the competitive application processor market.

In addition, Imagination continues to build out the portfolio of MIPS32 M-class CPUs, by adding the M6200 and M6250, two new M-class CPUs for microcontroller and deeply embedded 32-bit applications.

Smaller, more efficient and more secure 64-bit

MIPS P6600 implements the MIPS64 Release 6 architecture and carries a number of useful features focused on delivering peak performance, reduced area and low power consumption for a range of applications, including mobile, home entertainment, networking, HPC or industrial and embedded computing.

Building on and enhancing our 32-bit P5600 design, P6600 combines a deep 16-stage pipeline with multi-issue, Out-of-Order (OoO) execution to deliver outstanding computational throughput for today’s complex software workloads.

MIPS P6600 also includes best-in-class branch prediction and our load/store instruction bonding mechanism, two technologies that provide a clear-cut boost in real-world workloads while keeping silicon area and power consumption in check.

MIPS P6600 - MIPS64 CPU P-class Release 6_f The internal architecture of the MIPS P6600 64-bit CPU

Like the P5600 before it, MIPS P6600 is an OmniShield-ready design that supports full hardware virtualization and enhanced security features. This P-class Warrior CPU can handle up to 15 guest operating systems running simultaneously in fully isolated and trusted environments; this unprecedented level of scalability for virtualization and security gives the MIPS Warrior family another unique advantage in the battle for supremacy in the processor space.

P6600 also packs a super-fast SIMD engine for accelerating multimedia processing; you can read this article for more information on how the MIPS SIMD Architecture (MSA) has been used for efficient VP9 decoding.

System designers can use this new P-class Warrior CPU in configurations that range from single to hexacore clusters. The figure below shows a block diagram of the MIPS P6600 Multiprocessing System (MPS) that includes a Coherence Manager (CM2) with integrated L2 cache for a more streamlined data flow.

MIPS P6600 - multiprocessing system P-class_fMIPS P6600 can be integrated in hexacore SoCs

Each cluster implements per-CPU dynamic control of voltage and/or frequency, leading to even more significant gains in performance and power management.

32-bit processors for microcontroller and deeply embedded applications

M6200 and M6250 are enhancements of microAptiv UC and UP, respectively. Capable of operating at 30% higher frequency, both processors include:

  • Tightly coupled memory (TCM) for high-performance applications
  • An interrupt controller supporting up to 256 interrupts
  • The MIPS DSP Module Revision 3 as a configurable option, providing a high level of digital signal processing capabilities and SIMD support.
  • ECC and parity protection on instruction and data memories as a configurable option for increased reliability
  • A new APB interface enabling JTAG, multicore and mixed core debugging

These M-class processors are 6-stage pipeline designs that implement the MIPS32 Release 6 architecture and also include support for the microMIPS32™ ISA, a set of optimized 16-bit and 32-bit instructions that provide a significant reduction in code size with a performance equivalent to MIPS32.

MIPS M6200 is a 32-bit M-class CPU designed for microcontroller and embedded devices that run real-time operating systems; the processor includes an SRAM controller and 64-bit instruction and data SRAM interfaces.

  MIPS M6200 - MIPS32 MCU M-class Release 6 The internal architecture of the MIPS M6250 microcontroller

MIPS M6250 is a 32-bit M-class CPU designed for microprocessor devices that require Linux capabilities; it includes a high-speed 64-bit AXI bus interface, a Memory Management Unit (MMU), data and instruction cache controllers, and support for eXtended Memory Addressing (XPA) to 40-bit physical address space (up to 1 TB of system memory).

MIPS M6250 - MIPS32 MPU M-class Release 6

The internal architecture of the MIPS M6250 microprocessor

M6200 and M6250 are configurable and fully synthesizable solutions for devices requiring a high level of performance efficiency and small silicon area including wireless or wired modems, GPU supervisors, flash and SSD controllers, industrial and motor control, advanced audio and more.

The path ahead

Release 6 is based on a fixed-length, regularly encoded instruction set, and uses the same load/store data model that established MIPS as the most sophisticated RISC architecture in the CPU IP industry.

Release 6 also represents the foundation for the P6600, I6400, and M6200/M6250 processors, and provides a seamless upgrade path from previous offerings by incorporating powerful features, standardizing privileged mode instructions, and supporting past ISAs. Release 6 is streamlined to support optimized execution of high-level programming languages: arithmetic and logic operations use a three-operand format, allowing compilers to optimize complex expressions formulation. Availability of 32 general-purpose registers enables compilers to further optimize code generation by keeping frequently accessed data in registers.

mips_arch_history_11_nThe evolution of the MIPS architecture

Moving forward, we are committed to expanding our CPU roadmap by providing highly competitive designs that address the needs of SoC designers.

If you happen to be in China in November and want to hear the latest news from Imagination, make sure you register for our Imagination Summits in Beijing or Shanghai. Mark Throndson, director of business development for the MIPS BU, will be there presenting MIPS CPUs: Differentiating the Next Wave of Innovation.

What do you think about our MIPS Warrior family? Are you excited about the new 64-bit and 32-bit MIPS CPUs launched this year? Leave us a comment in the box below and follow us on Twitter (@ImaginationPR and @MIPSGuru) for the latest news and announcements from Imagination, our partners and licensees.

About the author: Alex Voica

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Before deciding to pursue his dream of working in technology marketing, Alexandru held various engineering roles at leading semiconductor companies in Europe. His background also includes research in computer graphics and VR at the School of Advanced Studies Sant'Anna in Pisa. You can follow him on Twitter @alexvoica.

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