One of the highlights of this week’s Linley Group Processor Conference 2013 is the official launch of the MIPS P5600 CPU IP core, the first member of the highly anticipated MIPS Series5 ‘Warrior’ CPU family from Imagination. The ‘Warrior P-class’ P5600 CPU IP core is a ‘best in class’ processor that addresses all four aspects that matter in mobile: efficiency, performance, area and features.
Leading performance delivered efficiently
The MIPS P5600 core has been designed to be a leader in high performance and power efficiency for 32-bit CPU IP. It offers 1.2 – 2x more system performance than its proAptiv predecessor in a similar mobile-focused power envelope, and supports peak frequencies above 2GHz on TSMC’s 28HPM process node.
Here’s a breakdown of what to expect from the MIPS P5600 CPU:
- Industry-leading single thread performance for high-end 32-bit CPUs (exceeding 5 CoreMark/MHz and 3.5 DMIPS/MHz, per core) at significantly lower power than its competitors
- Up to 30% area savings at the cluster level and 40% savings at the core level relative to similar performance competition, enabling it to achieve higher performance at reduced area
- A comprehensive feature set that includes virtualization, 128-bit SIMD, 40-bit eXtended Physical Addressing (XPA), scalable security, and more
The MIPS P5600 IP core is a balanced design that uses techniques such as load/store bonding, reading registers after issue (so no reservation station logic is required), and right-sized schedulers to efficiently achieve maximum utilization of the 16-stage pipeline and its superscalar, multi-issue out-of-order microarchitecture.
In addition to this high-performance pipeline and new features of 128-bit SIMD, virtualization, and XPA, the MIPS P5600 CPU has additional attributes designed to execute large, highly complex workloads, including:
- Large (> 1000 entry) TLB resources
- Best in class, advanced branch prediction mechanisms
- Enhanced Virtual Addressing (EVA) for more flexible usage of virtual address space, providing easy and efficient use of memory for larger footprint Linux implementations
MIPS P5600 highlights: EVA and XPA, the MIPS SIMD Architecture (MSA) and full hardware virtualization
MIPS P5600 implements EVA and XPA, two technologies that have been created to stretch the limits of traditional 32-bit architecture addressing in response to the increasing code size footprints of mobile and connected consumer devices. But they go well beyond the needs of those segments.
XPA is a new feature which extends the amount of addressable physical memory in devices to a maximum of 1 Terabyte, offering larger address space for applications that might need it. While the P5600 CPU was designed first and foremost for the needs of application processing in smartphones, tablets, DTVs and connected consumer devices, the performance/power profile and extensive feature set extend the reach of this CPU core into additional markets , including a variety of networking applications such as residential gateways, 802.11ac routers, CPE modems, microservers, and various functional network appliances.
MIPS P5600 is the first ‘Warrior’ CPU to implement three new features of significant relevance for modern processors: SIMD, hardware page table walking, and hardware virtualization.
The MIPS SIMD Architecture (MSA) features 150+ instructions, and was designed for use and code development in high-level languages such as C++ or OpenCL. As an example, the MIPS SIMD instruction set directly covers 100% of all compiler vector operations in the gcc compiler toolchain, which also leads to maximum auto-vectorization benefits on existing code. The instruction set covers integer/fixed and floating point arithmetic, permute and arbitrary shuffles on vectors and arrays, compare/convert functions, clever branching, and more. It supports a range of data types for high-performance multimedia applications including 8-, 16-, and 32-bit integer/fixed-point and 16-, 32-, and 64-bit floating point formats compliant with the IEEE-754 2008 standard. In addition, it provides a unique, faster exception model which means less work is required for exception processing.
On the virtualization side, MIPS P5600 implements full hardware virtualization, with support for many more than two independent operating systems running as guests, with no modification, fully isolated from each other. It includes features that address virtualization needs at the system level, including virtualized I/O and interrupt processes per execution environment. Virtualization has traditional use in servers needing many nodes operating separately in parallel, but the use of this technology is expanding into an increasing variety of applications. It can also be used for mixed mode Linux and real-time environments in separate domains, with open source application processing in one, with real-time, latency sensitive tasks running in another, with QoS/priority.
Current security solutions in phones and other connected consumer devices are limited. Unlike the limited choice provided by competitors between one secure and one insecure world, with MIPS there is a choice of numerous secure worlds. The isolation of each virtualized execution environment from the next is one key for security solutions going forward. Technology supporting multiple security contexts lays a foundation for building comprehensive and scalable security solutions that address the needs for next generation mobile and connected devices, enabling them to access secure content from multiple providers, make secure payments, and ensure identity protection across multiple applications and content sources.
Meet the MIPS P5600 hexacore coherent processing system
Imagination has designed the P5600 CPU to work in a fully coherent multicore system that can include up to six individual processors per single cluster, achieving 35,000 DMIPS and 50,000 CoreMark at 1.7 GHz. The diagram below features all the elements required to create a complete, fully functional CPU cluster:
- An Enhanced Coherence Manager with an integrated L2 cache controller
- Up to two IOCU blocks with secure I/O processes per virtualized operating domain
- A Global Interrupt Controller that supports virtualization and 256 system interrupts
- A Cluster Power Controller which features per-core clock gating and voltage domains
- A PDtrace block for cluster level program and data tracing
P5600 is the first core in a wave of Series5 ‘Warrior’ CPUs that will bring our pure RISC architecture across a range of 32-bit and 64-bit variants with a focus on superior performance efficiency for apps processors, real time CPUs, MCUs and other embedded offerings.
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