Larry Lapides, VP of Sales at Imperas, is here to tell you more about the collaboration between Imperas and Imagination as well as the wide range of solutions available for MIPS CPUs.
You are probably aware of Imperas as the provider of the technology behind the IASim product, the instruction accurate simulator for MIPS cores. You may not be so familiar with other Imperas products and the Open Virtual Platforms (OVP) technology. So here is an update.
A lot has been happening in OVP for the MIPS world. Models of the latest MIPS Warrior IP cores – P5600 and M51xx – are now available. The EPKs of the MIPS-based platforms were announced and are available. We also announced that Kyma Systems used Imperas tools and models to port the KVM hypervisor to MIPS. Also, at the end of February, we will be at the Embedded World 2015 conference presenting a paper about SMP simulation performance using parallel simulation acceleration. While the paper is about simulation technology, and not about MIPS-specific support, this technology certainly applies to MIPS-based virtual platforms.
New models for MIPS Warrior CPUs
Models of the MIPS P-Class and M-Class Warrior CPU IP cores from Imagination Technologies have been released by Imperas and OVP. The models of the P5600 and M51xx processor IP cores, as well as models of other MIPS processors, work with the Imperas and OVP simulators, including the QuantumLeap parallel simulation accelerator.
The processor core models and example platforms are available from the Open Virtual Platforms website. The models are also supported in the Imperas M*SDK™ advanced software development tools. In addition, the Imperas M*SDK and M*DEV™ products support the use of the Imagination Codescape Debugger for embedded software debug.
MIPS Extendable Platform Kits (EPKs)
Extendable Platform Kits™ (EPKs™) for MIPS CPU cores are now available. They are based on the functionality of Imagination’s MIPS FPGA evaluation platforms, enabling users to simulate MIPS-based systems using Imagination’s reference platforms. EPKs provide a base, a known good starting point, for users to extend the functionality of the virtual platform, to closer reflect their own platform, by adding more component models, running different operating systems or adding additional applications.
EPKs are virtual platforms (simulation models) of the target devices, including the processor model(s) for the target device plus enough peripheral models to boot an operating system or run bare metal applications. There are two generic flavors of the EPKs for MIPS, one targeting full operating systems, such as Linux, and one which focuses on Real Time Operating Systems (RTOS) such as Mentor Nucleus.
OVP models of the MIPS processor cores are included in the EPKs, and for those MIPS processors which support multiple cores, SMP Linux is supported for that EPK. For all of these initial EPKs for MIPS, many of the peripheral components of the platform are modelled, including the Ethernet component. The semi-hosting capability of the Imperas virtual platform simulator products enables connection via the Ethernet component from the EPK to the real world via the x86 host machine.
MIPS and Kyma
Recently Imperas announced that Kyma Systems has been successfully using the Imperas M*SDK™ product for virtual platform-based development of hypervisors. M*SDK enabled porting of the KVM hypervisor to support the latest MIPS cores which include hardware virtualization extensions. The OS and CPU-aware tools included with M*SDK also enabled more comprehensive and faster testing of the hypervisor.
The KVM hypervisor is included with standard Linux distributions. Initially, Kyma ported KVM to the MIPS32® Release 2 architecture using trap and emulate technology. With the transition to the MIPS32 Release 5 architecture, including the addition of hardware virtualization extensions to the Warrior P-class P5600 and M-class M5150 families, KVM for MIPS was re-developed to take full advantage of those virtualization instructions.
Embedded World, February 24-26, Nuremberg, Germany
Embedded World takes place in Nuremberg, Germany (February 24th to 26th). Imperas is presenting a paper titled “Parallel Simulation Accelerates Embedded Software Development, Debug and Test” in Session 23, Tuesday at 14:30. While we do not have a booth at the show, our partners Imagination Technologies – MIPS again! – will be showing some exciting demos at their booths. You can also contact us to arrange a demo separately with us.
Here is the abstract of the paper we will be publishing at Embedded World:
For any simulation technology, the key factors for usability are performance and controllability/observability. For instruction accurate virtual platforms, the controllability and observability have been successfully addressed in various ways, including using APIs for the processor models and tools integrated in the simulation environment. In the area of performance, where near real time simulation performance is required, virtual platforms have been limited to single thread execution because of the need for determinism in the simulation. This need is driven by the loss of many of the key benefits of controllability and observability if the simulation is not repeatable. While multiple threads on multiple cores of the host x86 PC offer the hope of performance improvement, the overhead for synchronizing multiple simulation execution threads to maintain deterministic simulation results has cancelled out any performance gains realized by parallelizing the simulation.
A new synchronization algorithm has been realized, with much lower overhead, so that significant performance gains have been achieved. Performance gains of over 2x have been achieved for symmetric multiprocessor (SMP) systems simulating on a 4-core host machine, while performance gains of over 3x have been achieved for asymmetric multiprocessor (AMP) systems. The same principals have also been applied to accelerating the performance of virtual platforms where the performance bottleneck is one or more of the models used for accelerating specific applications such as image recognition.
For more information about Imperas and our solutions for MIPS CPUs, you can contact us at info [at] imperas.com. Thank you for your continued support of Imperas and Open Virtual Platforms!Follow @ImaginationTech