The Ensigma Wire-Speed Switching and Routing (WSP) processor is a highly scalable and configurable embedded processor, enabling network connectivity, switching and routing. It is part of the Ensigma networking IP portfolio. With fiber to the home, node, basement, the functionality and the complexity of a Gateway Processor and Ethernet Switches increases significantly. The current generation gateway architectures in CPE are not addressing multi gigabit data rate with the growing functionality. These advanced architectures would need to;

  • Route Multi-gigabits of data
  • Provide sophisticated Quality of Service for applications like IPTV, VoIP
  • Handle very high number of flows
  • Ultra low cost device adaptable to mass markets
  • Needs to be highly programmable for changing requirements
  • Enable VPN, deep packet inspection to protect against attacks

 

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Ensigma’s Wire-Speed Switching and Routing (WSP) Solutions are highly scalable and configurable for various applications, enabling network connectivity, switching and routing. The engines offer complete offload of TCP/IP processing at hardware level to achieve higher data rates without burdening the host processor.

The WSP Processor architecture guarantees wire speed secure routing of any size packets between Gigabit Ethernet ports. The architecture is highly scalable for multiple Ethernet ports or peripherals with other protocols like ATM and is scalable for GPON and GEPON architectures. The hardware/software partitioning and the partitioning of software between Host Processor and Embedded modules ensure that WSP software can be very easily integrated into customer’s existing software.

WSP is a highly programmable processor. The architecture has various hardware blocks like QoS engine to achieve scalable and guaranteed performance. Functions like packet classification, deep packet inspection and modification are programmable using multiple 32-bit RISC engines (Class). The architecture has hardware assists for scheduling and reordering packets to the programmable engines. The blocks are connected using a proprietary bus for optimal throughput and highest performance with smallest area. The architecture provides separate busses for data transfers and control packet communication. It provides flexible performance that scales with internal memory and packet classification performance. The architecture is suited to low cost home-gateway SoC and shares a single SDRAM with the on- chip host.

The Classifier (CLASS) module is the heart of the architecture. It is a multi-processor module with hardware assists for packet processing functions of classification and Layer -3 modifications like NAT. The number of processing elements required in an implementation is dependent on the packet processing rate. The number of PE’s is scalable from 1 to 8 with very minimal degradation in cumulative performance.

The architecture has hardware based Buffer Management and supports Jumbo frames and IP/Ethernet Multi-cast without buffer copies.

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Software Architecture

The WSP architecture is a fast-path/slow-path state full architecture. The hardware blocks and the Processing Elements (PEs) in the Classifier block implement the fast path and the Host processor performs the slow-path.

The Ensigma WSP software includes the fast path code, the adaptation of the Linux kernel using net filters etc and the drivers to configure the hardware. The firmware and the software supports Linux IP Contracts and ALGs implementing firewall functions etc.

The API for the low level blocks is provided such that the integration is facile with any operating system. The software organization is as below and it is color coded to indicate the modules that are modified from standard Linux and the modules that are developed by Imagination.

Performance and Tools

Ensigma’s provided tools are used to determine the number of Processing Elements, Internal memory required and the external Memory bandwidth required for the processing.

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Protocols Supported

The WSP Solution supports various protocols in the networking Stack. Additional protocol support can be provided as a customization of PE Code.