Samsung Electronics president Young Sohn was at the Internet of Things World conference yesterday in San Francisco to introduce a new family of low-power chips designed for the next generation of IoT devices.

One of the new chips presented on stage is called ARTIK 1 and features a MIPS32-based, dual-core application processor, flash storage, a crypto engine and Bluetooth Smart radios for communication.

Samsung ARTIK 1 - MIPS microAptivThe Samsung ARTIK 1 chip is designed for wearable and IoT devices

Delving into the underlying architecture of the CPU cluster, we find two MIPS microAptiv processors: one configured for high-performance workloads and clocked at 250 MHz, and a low-power variant at 80 MHz. The modified diagram below highlights the two MIPS microAptiv CPUs at the heart of the ARTIK 1 chip:

Samsung ARTIK 1 architecture - MIPS microAptivSamsung ARTIK 1 key module components

Here is what the official page from Samsung says about the ARTIK 1 processor:

ARTIK 1 has the world’s smallest form factor (12mm x 12mm) in its class. Aimed especially at power-sensitive devices, ARTIK 1 provides weeks of use on a single charge. Its hardware includes a 9-axis motion sensor with gyroscope, accelerometer and magnetometer, as well as Bluetooth low energy connectivity. With a feature set tailored for wearables and IoT end nodes, ARTIK 1 is a mobile workhorse.

MIPS microAptiv quick facts

Ticking inside the ARTIK 1 chip, microAptiv is part of the award-winning Aptiv family and implements a five-stage pipeline architecture; here is how the two flavors above differentiate:

  • microAptiv UP features a cache controller and a Memory Management Unit (MMU) for embedded systems that run rich operating systems.
  • microAptiv UC includes a Memory Protection Unit (MPU) for fast execution of real-time operating systems

MIPS microAptivMIPS microAptiv implements a high-performance architecture for embedded applications

Samsung also presented plans for a complete datacenter-to-device software infrastructure designed around security. microAptiv features a secure debug interface which ensures a high level of security, and can provide added hardware-assisted safety for the main application processor.

MIPS microAptiv CPUs are based on an elegant RISC architecture which achieves better performance at lower frequencies and in a smaller area compared to competing solutions. For embedded and microcontroller-type applications, MIPS microAptiv offers class-leading performance: 1.7 DMIPS/MHz and 3.6 CoreMark/MHz.

microAptiv_performancemicroAptiv delivers superior DSP performance

Application developers will also benefit from a significant boost in DSP operations too (e.g. voice processing) since microAptiv offers up to 2.56x higher DSP performance versus the competition.

Finally, microAptiv CPUs support microMIPS, a code compression ISA designed to reduce memory requirements for embedded systems.

Looking to build a next-generation IoT chip?

Samsung isn’t the only company that recognizes the benefits of MIPS for IoT applications. Here are other recent examples of MIPS MCUs being used in embedded systems:

If you’re looking to design next-generation solutions for connected devices, the combination of our MIPS M-class MCUs and Ensigma Whisper RPUs is a perfect fit. Together with our industry-leading FlowCloud software framework for IoT and cloud development, we can provide a full technology IP platform that enables our customers to innovate while delivering superior user experiences and true product differentiation.

Make sure you also follow us on Twitter (@ImaginationPR, @MIPSguru, @MIPSdev) for the latest news and announcements on sensors and wearables and keep coming back to our blog.

About the author: Alex Voica

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Before deciding to pursue his dream of working in technology marketing, Alexandru held various engineering roles at leading semiconductor companies in Europe. His background also includes research in computer graphics and VR at the School of Advanced Studies Sant'Anna in Pisa. You can follow him on Twitter @alexvoica.

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