Earlier this month, Lantiq introduced the new XWAY™ VRX300™ chipset that incorporates a multi-threaded MIPS CPU. The XWAY VRX300 joins the existing MIPS-based members of Lantiq’s AnyWAN™ system architecture to offer an integrated, high performance VDSL chipset family delivering data rates of up to 200 Mbps for gateway designs.

The XWAY VRX300, an ultra-fast VDSL2 chipset from Lantiq

The new VRX300 platform pairs Lantiq’s advanced XWAY GRX300 communications processor with the XWAY VRX318 VDSL Transceiver chip to offer a flexible solution for the growing VDSL market.

VDSL is already proving to be a viable solution for delivering HDTV, VoIP and Internet services over existing wiring used for analogue telephone services. In Germany, VDSL coverage includes over 50 major cities and 750 smaller cities and towns; in the UK customers might be familiar with BT’s Openreach which offers downstream bit rates of up to nearly 80 Mbit/s.

MIPS Lantiq XWAY VRX300 MIPS Lantiq XWAY VRX300

Lantiq’s XWAY VRX300 chipset family provides a fully integrated solution for ADSL2/2+/VDSL2 802.11n MIMO/VoIP gateway/router systems

Lantiq therefore has a very strong potential to keep growing in this market, as demand for VDSL/VDSL2 (Very-high-bit-rate Digital Subscriber Line) is set to more than double, from about 22 million in 2012 to 57 million in 2016 according to IHS iSuppli.

MIPS – leading CPU IP for networking

We are very excited to see Lantiq deploy their whole range of AnyWAN solutions based on our industry leading MIPS32 CPUs. Thanks to the highly-efficient MIPS architecture, Imagination is able to deliver high performance CPU IP cores that perform very well in real world usage scenarios, yet always keep power consumption low.

MIPS32 and MIPS64-based CPUs have repeatedly proven to deliver energy efficient networking solutions, having been successfully integrated into a wide range of platforms, from customer premises equipment (CPEs) to data center and enterprise products.

Furthermore, certain MIPS cores implement a series of unique architectural features that are designed to exploit multi-threading in embedded applications.  By allowing multiple threads to be handled in parallel, our silicon partners benefit from the ability to mask system stalls created by memory latency. MIPS’ implementation of multithreading has been shown to deliver 20-40% gains in system performance and cost savings, with only a small increase in area.

MIPS interAptiv CPS

The diagram above shows a typical implementation of multicore and multithreading MIPS technologies in a unified, coherent processing system (CPS)

As most embedded platforms are designed to run real-time applications, MIPS CPUs offer users the ability to create throughput-flexible systems by allocating dedicated processing bandwidth to real-time tasks. This type of dynamic load balancing and scheduling provides a guaranteed QoS rate and avoids resource starvation in a power efficient way.

Meet interAptiv – the multithreaded, multicore CPU designed for all your embedded needs

interAptiv is a part of the latest generation of multithreaded, multicore MIPS32 processors. With interAptiv, we’ve improved both our per-thread and per-core performance and added essential enhancements for error correction and power management, bringing its performance efficiency a class above competing CPU IP cores.

interAptiv can be used in various multi-cluster configurations which have been fine tuned to decrease power consumption. To achieve this, we’ve implemented a series of advanced power management techniques both at the cluster and core levels to help SoC designers monitor and control their system’s energy efficiency.

mips interAptiv architecture

Similar to the multi-threaded core used by Lantiq, interAptiv is one of the very few embedded CPUs that supports multithreading. It offers two virtual hardware threads (VPEs) which appear as two complete processors to an SMP operating system. Multithreading improves power consumption because it doesn’t have to perform speculative memory fetches to reduce latency. The pipeline can therefore finish a given workload faster because it doesn’t have to wait for a certain thread to receive data back but can perform a context switch to a different execution thread.

interAptiv’s superior performance has been reflected both in real world scenarios as well as benchmarks. For example, the EEMBC CoreMark score for single thread performance on interAptiv  core is 2.6 CoreMark/MHz and, using multithreading, nearly 25% higher. EEMBC has certified a score of 3.2 CoreMark/MHz on an interAptiv CPU with two hardware threads per core. An additional 10% or more performance can be expected in the near future via enhancements to the gcc compiler toolchain for the interAptiv family.

For more information on our Aptiv line of processors and future updates on our MIPS architecture and roadmap, follow us on Twitter (@ImaginationPR and @MIPSGuru) and keep coming back to our blog.

About the author: Alex Voica

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Before deciding to pursue his dream of working in technology marketing, Alexandru held various engineering roles at leading semiconductor companies in Europe. His background also includes research in computer graphics and VR at the School of Advanced Studies Sant'Anna in Pisa. You can follow him on Twitter @alexvoica.

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