MIPS microAptiv is the smallest, lowest power CPU family available from Imagination.

The microAptiv cores also have higher performance than competing converged microcontroller/DSP solutions in their class, delivering a Dhrystone of 1.57 DMIPS/MHz, and a CoreMark of 3.44 CoreMark/MHz in microMIPS mode.

With a growing ecosystem of supported third partner products, and a comprehensive set of MIPS development tools, microAptiv provides a complete environment to accelerate SoC design and reduce time to market.

microAptiv is a high-performance, compact processor that features advanced DSP capabilities. microAptiv can be licensed in two configurations:

  • a microprocessor (MPU) with a Memory Management Unit (MMU) and cache memories
  • a microcontroller (MCU) with a Memory Protection Unit (MPU)

MIPS microAptiv UC Core

microAptiv MCU

A cacheless implementation and superset of the MIPS32® M14K core for microcontroller applications.

MIPS microAptiv UC Core

microAptiv MPU

A superset of the MIPS32® M14Kc core with a cache controller and a Memory Management Unit (MMU) to facilitate embedded systems designs executing rich operating systems which manage virtual memory.

MIPS microAptiv features

Advanced DSP features

The microAptiv cores are enhanced with the addition of the MIPS DSP Application Specific Extension (ASE) release 2. microAptiv cores retain all of the features available in the M14K core, including the microMIPS code compression ISA and MCU ASE which deliver real-time performance and cost advantages in the development of microcontroller and embedded systems designs.

The DSP ASE r2 provides the microAptiv MCU core with high performance, single cycle throughput DSP and SIMD capabilities to address the requirements of a broad range of embedded applications requiring more signal processing functionality. These applications include industrial/motor control, smart meters, automotive, storage, mobile communications and security.

Secure debug

In addition, the microAptiv MCU core integrates a Memory Protection Unit and a Secure Debug functionality, features that can be used to advantage in systems requiring a high level of security.

microAptiv cores offer a significant amount of configurability, including the choice of operating in MIPS32-only mode, MIPS32+microMIPS mode or microMIPS only mode.

The debug capabilities of the microAptiv cores have been further enhanced with the addition of a low cost 2-wire cJTAG option (IEEE standard 1149.7).