Imagination’s MIPS32® architecture is a highly performance-efficient, industry standard architecture that is at the heart of billions of electronic products, from tiny microcontrollers to high-end networking equipment. It provides a robust instruction set, scalability from 32-bits to 64-bits, a broad-spectrum of software development tools and widespread support from numerous partners and licensees.

The MIPS32 architecture provides seamless upward compatibility to the 64-bit MIPS64® architecture, bringing powerful features, standardized privileged mode instructions, and support for past ISA versions. The MIPS32 architecture incorporates important functionality including SIMD (Single Instruction Multiple Data) and virtualization. These technologies, in conjunction with technologies such as multi-threading (MT), DSP extensions and EVA (Enhanced Virtual Addressing) enrich the architecture for use with modern software workloads which require larger memory sizes, increased computational horsepower and secure execution environments.

The MIPS32 architecture is based on a fixed-length, regularly encoded instruction set and uses a load/store data model. The architecture is streamlined to support optimized execution of high-level languages. Arithmetic and logic operations use a three-operand format, allowing compilers to optimize complex expressions formulation. Availability of 32 general-purpose registers enables compilers to further optimize code generation for performance by keeping frequently accessed data in registers.

A set of registers reflects the configuration of the caches, MMU, TLB, and other privileged features implemented in each core. By standardizing privileged mode and memory management and providing the information through the configuration registers, the MIPS32 architecture enables real-time operating systems, other development tools, and application code to be implemented once and reused with various members of both the MIPS32 and the MIPS64 processor families.

Flexibility of its high-performance caches and memory management schemes are strengths of the MIPS architecture. The MIPS32 architecture extends these advantages with well-defined cache control options. The size of the instruction and data caches can range from 256 bytes to 4 MB. The data cache can employ either a write-back or write-through policy. A no-cache option can also be specified. The memory management mechanism can employ either a TLB or a Block Address Translation (BAT) policy. With a TLB, the MIPS32 architecture meets Windows CE, Linux and Android memory management requirements.



MIPS Instruction Set Quick Reference


MIPS32 Architecture for Programmers: Release 6


MIPS32 Architecture for Programmers: Release 1-5