Embedded devices today—including smartphones, tablets, IP set top boxes, smart residential gateways and SSD storage—are delivering new levels of functionality, connectivity and application richness. These advanced-feature devices are in tremendous demand, and with this demand come unique challenges. SoC providers and OEMs must minimize costs in high volume production, meet aggressive performance requirements, support quality of service (QoS) for latency sensitive traffic, and manage power consumption, particularly in mobile applications that require ultra-low power. Striking that right balance of performance, power and cost in such high-volume mid-range applications has never been more of a challenge than it is today.
To address these challenges, SoC providers have several choices. Increasing a processor’s clock frequency provides a significant performance boost; however it is a less than ideal solution as it also greatly increases power consumption. Another alternative is to go multi-core, which distributes the processing load to achieve higher performance. This option however, may increase costs in terms of IP licensing, manufacturing (due to larger silicon die size), and power consumption.
A third option, included in the MIPS architecture and several MIPS cores including our new interAptiv™ core, is hardware multi-threading (MT). MT can make a single processor core appear to an SMP operating system like two separate cores. Furthermore, these two virtual processors could support multiple operating systems or a combination of an OS and a “bare metal” environment. In this case, the processing load is distributed across what appears to the operating system to be two cores. With a multi-threaded core, the increase in die size is relatively small and there is no need to pay a license fee or royalties for a second core. In the case of a multi-core system, MIPS’ 2nd generation Coherence Manager (CM2), which has an integrated L2 cache, improves multi-core performance by simultaneously reducing latency and increasing bandwidth. The CM2 supports up to four interAptiv CPUs or eight virtual processors in a single, fully coherent, multi-processor system.
Each multi-threaded MIPS core can support up to two VPEs which share a single pipeline as well as other hardware resources. However, since each VPE includes a complete copy of the processor state as seen by the software system, each VPE appears as a complete standalone processor to an SMP Linux operating system. For more fine-grained thread processing applications, each VPE is capable of supporting up to 9 TCs allocated across 2 VPEs. The TCs share a common execution unit but each has its own program counter and core register files so that each can handle a thread from the software.
The MIPS MT architecture also allows the allocation of processor cycles to threads, and sets the relative thread priorities with an optional Quality of Service (QoS) manager block. This enables two prioritization mechanisms that determine the flow of information across the bus. The first mechanism allows the user to prioritize one thread over another. The second mechanism is used to allocate a specified ratio of the cycles to specific threads over time. The combined use of both mechanisms allows effective allocation of bandwidth to the set of threads, and better control of latencies. In real-time systems, system-level determinism is very critical, and the QoS block facilitates improvement of the predictability of a system. Hardware designers of advanced systems may replace the standard QoS block provided by MIPS Technologies with one that is specifically tuned for their application.
Single-threaded microprocessors today waste many cycles while waiting to access memory, considerably limiting system performance. The use of multi-threading masks the effect of memory latency by increasing processor utilization. As one thread stalls, additional threads are instantly fed into the pipeline and executed, resulting in a significant gain in application throughput. Users can allocate dedicated processing bandwidth to real-time tasks resulting in a guaranteed Quality of Service (QoS). MIPS’ MT technology constantly monitors the progress of threads and dynamically takes corrective actions to meet or exceed the real-time requirements. A processor pipeline can achieve 80-90% utilization by switching threads during data-dependent stalls or cache misses. All of this leads to an improved mobile device user experience, as responsiveness is greatly increased