A few weeks ago Brian Bailey, the well-known technology editor for EDA at Semiconductor Engineering, kindly asked me to provide some comments in relation to a set of very interesting questions on the fate of Moore’s Law and the adoption of sub-20nm process nodes. You can find a selection of my answers, alongside opinions and thoughts from a slew of industry experts, in his recently published comprehensive article: Moore’s Law Tail No Longer Wagging The Dog. I would like to thank Brian for this opportunity and look forward to more articles from him on this topic; if you’re interested in my opinions on IP development in the context of Moore’s Law, please find my answers in full below.

Nanotechonolgy Research At University Of Albany 28nm is here to stay for high volume 32 and 64-bit mobile apps processors

One thing mentioned quite a few times at DAC this year is that Moore’s law has already ended for many people. They do not see the need to move to new nodes and the economics no longer favor it (major exclusions are apps processors and high-end computing/infrastructure). First off, do you agree with these statements?

High-end mobile and desktop processors will always go for the latest process nodes because at that level achieving ultimate performance efficiency is vital. These processors end up in devices which need to top benchmarks and are driven by a high-end feature set, therefore performance and power are critical factors which model design methodologies.

However, silicon vendors in the embedded market have historically relied on using proven process nodes which tend to lag behind high-end mobile and desktop. For example, a lot of microcontrollers today are still manufactured at 90nm or 45nm. When targeting mass volume markets, designing low cost processors becomes extremely important, therefore moving to the latest toolchain might not always make sense from a business perspective.

In the near future, we will probably see affordable mobile and wearable devices still using the established 28nm process node because it makes sense both from an engineering and business perspective. Furthermore, technologies like FD-SOI can breathe new life into 28nm. By offering improvements in performance and power, FD-SOI expands 28nm usability across new segment markets.

How does this affect IP developers?

Designing for low power has always been a priority for mobile. Imagination Technologies puts efficiency first whenever creating a new family of processors which in turns ensures that our silicon partners always get a solution that achieves the best PPA at any given process node.For example, we have included new technologies like PVR3C or PowerGearing in our latest generation PowerVR Rogue GPUs so system designers have to worry less about power-related issues like memory bandwidth.

Additionally, we have recently released Design Optimization Kits (DOKs) for our IP processors that have been extremely popular within our customer base. Our DOKs provide a flexible solution for system architects to optimize for power, performance and area and deliver substantial silicon PPA gains while reducing design cycle times. The first DOK we have co-developed with Synopsys has reduced dynamic power by up to 25% and area up to 10% for PowerVR Series6 GPUs.

We also maintain very close relationships with all foundries, including TSMC, GLOBALFOUNDRIES, UMC or SMIC; we’ve recently announced we are working with TSMC to drive industry-leading performance for PowerVR GPUs using 28HPM and 16nm FinFET technologies for next generation apps processors.

To stay competitive, design and architecture may become much larger differentiators than they were in the past. Will this enable additional companies to enter the market if cost is no longer a barrier to entry?

This is a very interesting point. The trend across hardware and software design right now is to create technologies that free the industry from historical ties to underlying ISAs. However, inherent architectural attributes remain important for dynamic compilation performance, how efficiently an architecture implements in silicon, and support for open standards and operating systems. The MIPS ISA features like single operation per instruction, simple addressing modes, no predicated execution or no integer condition bits translate into real world benefits that help system designers achieve higher performance and build high-end, superscalar, OoO (Out of Order) CPUs operating at high frequencies while keeping power consumption firmly in check.

mips_cluster_28nm A high-performance, three-way MIPS CPU cluster tapeout on GLOBALFOUNDRIES’ low-power 28nm-SLP process technology

We have recently seen a lot of interest from companies licensing MIPS CPUs for wearables. Innovation is ripe in this space and the unique features of our MIPS architecture have enabled some very interesting designs. One of them is Ineda Dhanush, an SoC implementing a concept called Hierarchical Computing Architecture (HCA). HCA is tiered multi-CPU architecture that can share peripherals and local memory so multiple CPUs can run independently and create a unified application experience for the user. Combining HCA with a ground-up designed modular SoC offers superior power optimization capabilities over what is available today.

Does it make sense to create a 28nm FinFET process? What other new technologies could be built into the existing nodes and how much advantage would they provide? Can 28nm be improved so that yields, tolerances and other factors be improved significantly?

I don’t think it makes sense to bring FinFET to 28nm. However, this doesn’t mean that innovation at this process node has to stop. For example, TSMC has recently introduced 28HPC, a low cost version of 28HPM. 28HPC is a leading technology for 64-bit apps processors that target the mid-range and entry-level market; it offers a high density 7-track library with improved power and routing efficiency, flexible channel length for low leakage designs and reduces chip area after place and route.

To give you an idea of how 28HPC stacks up against 28LP, this new process node offers better performance (1.26x), lower power (0.61x) and smaller area (0.9x). Moreover, it is compatible with 28HPC and can be easily re-calibrated for a range of PPA enhancements. The great news about 28HPC is that it goes beyond mobile – according to TSMC, it is set to become a leading process node for IoT applications.

If you want to know more about EDA, make sure you follow Semiconductor Engineering (@SemiEngineering) and Imagination (@ImaginationPR) on Twitter and keep coming back to our blog.

About the author: Alex Voica

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Before deciding to pursue his dream of working in technology marketing, Alexandru held various engineering roles at leading semiconductor companies in Europe. His background also includes research in computer graphics and VR at the School of Advanced Studies Sant'Anna in Pisa. You can follow him on Twitter @alexvoica.

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