14th February 2005

Imagination Technologies Debuts PowerVR MVDA2 Multi-Standard Video Decode Accelerator

IP Enables Advanced Mobile TV And Multimedia


London, UK: Imagination Technologies’ PowerVR division a market leader in embedded graphics, video and display technologies announces the availability of its PowerVR MVDA2 multi-standard video decode accelerator.

The PowerVR MVDA2 IP core accelerates all key video standards across a range of applications including mobile TV and handheld multimedia.

MVDA2 accelerates the decode of MPEG-2, MPEG-4, WMV8, WMV9 and H.264 video streams, at resolutions programmable up to 720 x 576, offloading inverse Zig-Zag, inverse Discrete Cosine Transform (iDCT), Motion Compensation and deblocking, the most costly stages in video decoding, from the CPU. The reduction in CPU load achieved is typically in excess of 80% for H.264, thereby allowing the system designer to target lower cost and lower power systems. This is of increased importance when performing quarter-pel motion compensation as used in modern video compression standards.

Deblocking can be performed either by directly accessing the macroblocks from the decoder hardware or by fetching them from system memory which allows it to be used for general video post-processing.

PowerVR MVDA2 in Detail
MVDA2 is available with a video decode acceleration driver which supports the acceleration of common video codecs through a single easy to use interface. The driver is available for Linux and WinCE platforms.

The MVDA2 core is configurable at synthesis time for 32 or 64-bit system bus widths. Power requirements are optimized by sophisticated power management techniques using register-level clock gating to ensure the lowest active and standby power.

A full rate H.264 Baseline profile stream decode can be achieved with the core running at less than 50MHz (CIF resolution: 352×288 pixels, 30 frames per second). SD resolution is also supported with a 100MHz clock frequency.

PowerVR MVDA2 is available as soft IP and ships with: synthesis scripts; an extensive verification test suite to ensure correct implementation of the design in a SoC; a hardware implementation guide; and a comprehensive programmer’s reference manual.


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