31st October 2007

Imagination Technologies META HTP Multi-Threaded Processor IP Core


October 31st 2007, Tokyo: Imagination Technologies a leader in mobile multimedia technologies for SoCs has announced its new META HTP multi-threaded processor IP core family as part of Multicore-Expo Japan today in Tokyo. Based on META2 architecture the latest generation of Imagination’s highly regarded META™ multi-threaded processor core technology, META HTP extends support for powerful Operating Systems (OS) and applications while providing faster speeds and new architectural enhancements.

The multi-threaded architecture of META HTP, which has been proven in silicon in millions of units, allows the overlapped execution of multiple threads, enabling multiple time-critical DSP-rich applications and non real-time general purpose tasks to run concurrently on the same processor, reducing power consumption and silicon area whilst increasing throughput beyond that of traditional processors so that one META HTP can replace multiple high performance RISC and DSP cores.

META HTP implements a longer pipeline, enabling it to achieve higher clock speeds ranging from 360 MHz in 130nm to 500 MHz in 90nm, and up to 700 MHz in 65nm process using standard cells together with high speed SRAM macros for cache. A longer pipeline would normally reduce benchmark performance per MHz; however META HTP includes additional architectural features to compensate including a return address cache and branch prediction table support. A four threaded META HTP delivers up to 1552 DMIPS in a 65nm process.

META HTP will be available with integer and DSP with optional full floating point that supports both 32-bit single precision and 64-bit double precision formats.

The META HTP processor family is code compatible with earlier members of the META processor family, and will also introduce Imagination’s Minim 16 bit instruction set, as used by Imagination’s META MTX1 for common instructions. This increases code density by typically 20-30% relative to the regular 32-bit instruction set. Code compatibility with earlier META processors provides a wide range of applications immediately available for audio, video, communications and other embedded SOC tasks.

Despite the advanced multi-threaded architecture of the META HTP, software creation follows the same development flow of a traditional processor. META HTP is supported by advanced CODESCAPE industry-proven development tools from Imagination Technologies supporting a wide range of advanced debug features such as real time non-intrusive trace.

Why Multithreading?
SoC devices are being designed for global products that offer multi-function capability, requiring multiple high speed data stream I/Os and peripherals while meeting tough system timing, power and performance constraints. With many competing demands on memory subsystems from multiple units including CPUs, DSPs, and GPUs, a processor’s potential throughput is greatly reduced by SoC memory latency. Traditional CPU solutions are not working only a processor designed for maximum latency tolerance provides an efficient solution.

For system management the META HTP processor is specifically designed for high performance real time operation at low clock speeds, making the best possible use of memory bandwidth and providing exceptional tolerance of system latencies.

META HTP’s multiple hardware threads are each a virtual processor operating in a parallel / overlapped manner with no context switching overheads. Each META HTP hardware thread can be RISC or DSP which is decided during synthesis and each virtual processor can run an independent OS, including Embedded Linux, Nucleus or Imagination’s own MeOS RTOS or they can run code natively.

Says Tony King-Smith. VP marketing at Imagination: META HTP’s scalable architecture has all the benefits of multi-processing but with less silicon resource and development complexity. And it is significantly lower cost than a multi-processor approach. Its unified architecture delivers both powerful DSP and general-purpose processing whilst the multi-threading ‘hides’ memory latency in SoC solutions. Our customers have proven the benefits of the META architecture in millions of shipping devices; META HTP takes that to a new level of performance whilst maximising the benefits of using multi-threading with tightly integrated peripherals and co-processors in next generation SoCs.

Latency tolerant ideal for SoCs
Traditional processors are often stalled due to multi-cycle memory latencies or unproductive whilst performing context switches in software under control of a multitasking RTOS. META HTP tolerates latency much better than other solutions. When one thread stalls, another may execute and there is zero overhead switching between threads so stall cycles are not wasted.

On each cycle one or more threads will execute depending upon the resource required by each thread, maximising central ALU and memory utilization. META HTP’s Superthreading allows threads to run simultaneously, provided they are not competing for the same resources, to perform more work per clock cycle.

Each META HTP thread’s capability is ‘software configurable’ and not ‘hardwired’, as in multi-processing, for greater flexibility. Imagination’s Automatic MIPS Allocation (AMA) technology makes threads easy to use and real-time aware when running multiple time-critical tasks.

Low Power, High Performance
META HTP is designed for low power. Superthreading allows more work per clock cycle so the SoC can run at lower clock speeds while AMA handles system load-balancing to meet processing deadlines. Fine-grain power management includes low-level clock gating, thread and resource scheduling to control clock gating operation and unused resources which are automatically ‘switched off’ cycle by cycle. As a result of these features META HTP processors can run at a far lower frequency than other processors for the same level of processing performance.

Efficient SoC Design with META HTP
SoCs can be made inherently more efficient by combining a real-time processor, running at ‘just enough’ speed, with specific co-processors for specialised tasks. The META HTP Coprocessor Interface supports up to eight read and/or write interfaces to allow threads to operate synchronously with other hardware modules. Each interface supports single-cycle synchronous 64-bit data exchange.

Imagination’s META HTP processor family also includes a broad range of audio decoders and audio enhancement algorithms. In combination with Imagination’s visual IP and communications IP core families, META HTP completes the range of functions required by even the most advanced multimedia SoCs.

Inside the META HTP IP Core
The META HTP has a rich DSP feature set capable of up to four 16-bit MACs/cycle, or two 32-bit MACs/cycle with a VLIW-like instruction template for complex DSP operations, combining four instructions in a single cycle.

META HTP features four-way set associative data and instruction caches and a thread-aware MMU able to support demand page virtual memory, as required by full featured OS, and optimised for Linux.

The META HTP debug features can be accessed through a high-speed non-intrusive JTAG connection requiring no debugging code to be present on the META HTP processor. The PC hosted advanced CODESCAPE Debugger can gain control of the META HTP core as it resets, allowing ROMless boot during code development, and provides a rich set of debugging features as well as initialisation of target system memory and peripherals.

Alongside the launch of META HTP, Imagination has also released the latest version of its highly successful META ATP multi-threaded processor core, based on the META1 architecture. The latest release of META ATP includes a series of enhancements including core code memory and real time trace support.

Papers
Imagination’s Jim Whittaker presented a paper, Synthesizable High-speed CPU Core Realized by Low Power Process at the Multicore-Expo conference and explored the tools available for META development in Answering the software development challenges of Multi-core systems at the co-located Embedded Processor Symposium Japan. Nikkei Electronics, a flagship magazine of Nikkei BP, has been producing the annual Embedded Processor Symposium every year since 2002 to address the emerging needs of embedded hardware and software designers.

About Imagination Technologies
Imagination Technologies Group plc (FTSE:IMG) a leader in semiconductor System on Chip Intellectual Property (SoC IP) creates and licenses market-leading embedded graphics, video and display accelerators, multi-threaded processors and multi-standard receiver technologies. These IP solutions are complemented by dynamic and extensive developer and middleware ecosystems.

Target markets include digital radio and audio; mobile phone multimedia; car navigation & driver information; personal navigation; UMPC and Mobile Internet Device (MID); digital TV & set top box; and mobile TV. Its licensees include leading semiconductor and consumer electronics companies.

Imagination has corporate headquarters in the United Kingdom, with sales and R&D offices worldwide.


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